The use of interposers is important for debug, signal measurement and validation of interconnects in memory systems. As speed increases, the effect of the interposer on signal integrity of the system grows, and cannot be ignored. It is important to understand the performance of the system after the interposer is added. Scattering parameters are a good way to capture the performance of the interposer. The S-parameter data can be used to interpret the performance characteristics, in system level simulation to evaluate jitter and eye opening, and to create de-embedding filters for oscilloscopes, essentially removing the influence of the interposer from the scope waveform. This paper will interpret multiport S-parameters for several memory interposer design cases. This will help the audience understand some of the performance characteristics that can be inferred from the S-parameters, as well as some of the interactions between the interposer and the device under test and probing system. From a system level design perspective, reviewing this data helps the engineer to have confidence in probing implementation, whether the engineer is designing or using a purchased interposer. This paper follows a DDR4 design case that will be carried forward to be used with deembedding information for a post-production oscilloscope measurement. Finally, VNA measured S-parameters of the fabricated interposer will be compared to the extracted preproduction S-parameters thus validating the S-parameter extraction process. This paper will progress through suggestions of how to relate frequency domain performance to physical design, physical characteristics versus edge rate, insertion and return loss values and interaction, linearity, the effects of probe and system noise, and through path performance effects on the complete system. The design and use of memory measurement interposers has to be carefully thought out to avoid performance degradation of the system under test, while at the same time providing accurate and repeatable measurements. This paper adds to existing interposer literature by offering a state of the art perspective for the design and use of an interposer for probing DDR4 memory packaging at speeds that are difficult to achieve. The effects of the physical structure of the interposer can't be ignored, so the careful designed of the interposer is needed to yield valid measurement results. This paper explores the challenges and solutions to successful interposer design.
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