Accurate IBIS-AMI Modeling of DSP-Based 56G Ethernet Transceivers Successful Hardware to Model Correlation

摘要

56Gbps/112Gbps PAM-4 PHYs are becoming the default technology for implementing 400G/800G network solutions. To accommodate such high data rates, most of the existing PHY designs have moved from PVT dependent and hard to scale analog architectures to more robust and flexible DSP implementations. This architectural shift has significant implications on simulation and modeling of High-Speed SerDes transceivers, with IBIS-AMI models. This paper highlights key concepts for accurate IBIS-AMI model generation and simulation of DSP-based transceivers and demonstrates the modeling performance through model simulation and silicon correlation.