A New Methodology for Developing IBIS-AMI Models

摘要

High speed serial link channel simulation is critical for system design and validation. The simulation must run fast while achieving adequate accuracy. Today, system vendors require Input/Output Buffer Information Specification Algorithmic Model Interface (IBISAMI) models long before silicon is available. To meet the demand, silicon vendors desire an efficient process for generating IBIS-AMI models efficiently and reliably. This paper first discusses the challenges facing the IBIS-AMI model development. Then it proposes a new methodology for AMI model generation, along with engineering trade-offs needed. The methodology and procedure this paper presents have shortened the development cycle over the previously used method for a 20nm 32Gbps Serializer-Deserializer (SerDes). The developed IBIS-AMI model was tested across multiple Electronic Design Automation (EDA) platforms. Detailed modeling techniques for accuracy and speed improvement are discussed throughout the paper.