Reflection Cancellation Design With Embedded Resistor for DDR Memory System

摘要

An innovative design is proposed in this paper to address the multi-load DDR command/address/control (CAC) signals' reflection problem without requiring additional layout spacing than existing memory design. In this design series resistors are inserted in the memory chip branches of the fly-by topology, which cancel the reflection in one direction. These resistors are implemented by embedded resistor technology to break the limitation of layout spacing. The simulation and validation results show this design can effectively optimize the margin of the CAC signals and help system to achieve higher operation speed and heavier loadings.