The paper reports the latest advancement in ultra-high bandwidth die-package-PCB co-design for 56G NRZ serdes devices. The significance of the work comes from the use of multiple recent technologies in super-low DF dielectric material, metal surface treatment, laser-drill capable and FPGA size scale thin-core substrate that is previously deployed in small mobile devices only. Moreover, the engineering achievement in die-package-PCB co-design is proven pivotal to the low power serdes system. The entire work is demonstrated with an 8-lane TX/RX 56G NRZ prototype device. The result becomes the cornerstone to future 100G serdes FPGA packages.
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