Analog RF Model Development with Verilog-A

摘要

Over the past several years, analog hardware description languages (AHDLs) have gained increasing acceptance in the areas of analog and RF circuit simulation. The widespread adoption of these standardized languages promises to bring substantial benefits to analog model developers and to the users of analog simulation tools. In this paper, we examine the applicability of the Verilog-A hardware description language for analog RF modeling tasks, with an emphasis on issues of importance to circuit designers, device modeling specialists, and simulation tool developers. The current capabilities and limitations, as well as future directions, are discussed.