SystemC and SystemVerilog for Electronic System-Level (ESL) Design Class # ESC-470

摘要

The development of today's electronic products poses many design and verification challenges. To deal with the inherent complexity of the combined hardware and software aspects of these embedded systems, academics and companies alike are exploring new methodologies under the umbrella of electronic system-level (ESL) design. Some argue passionately that all development should be done in C or C++; some insist that the hardware development languages (Verilog and VHDL) can be extended to do the job, while others are proposing completely new languages to address the problem. This paper takes a practical, real-world view and presents the case that a well-integrated solution based on two existing, standard languages-SystemC and SystemVerilog-is all that's needed for the effective design and verification of embedded systems. SystemC, a language based on C++ ideal for high-level modeling of systems, and SystemVerilog, a complete hardware design and verification language, span the scope of design abstractions needed for today's complex products. When tightly integrated in a tool flow, the combination of these two languages enables a flexible mix of high-level and cycle-accurate portions of the design, providing mixed-level verification from the most abstract architectural models through RTL and even gate-level implementations. Moreover, SystemC and SystemVerilog are both widely used today, standardized by IEEE and other industry organizations, and supported by a broad range of tools from EDA vendors. No other existing or proposed approach has these same attributes-the right embedded design and verification solution spanning ESL and RTL is here today.