Optimisation of Passive System Components to Minimise DC Circuit Breaker Stresses in Multi-Terminal Systems

摘要

HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system.