A Novel Parallel Multiply And Accumulate (V-MAC) Architecture Based On Ancient Indian Vedic Mathematics

摘要

In this paper new parallel multiply and accumulate ("MAC") is proposed based on algorithm of ancient Indian Vedic Mathematics for high speed applications. In the proposed architecture all bits of operands (multiplier and multiplicand) and accumulator are presented in parallel. The multiplier concurrently adds the partial products bits generated with the accumulator bits. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -4. The present paper relates to improvement in speed/area over MAC architectures implemented in digital signal processors. In FPGA implementation it has been found that the proposed parallel Vedic multiply and accumulate (V-MAC) is faster than multiply and accumulate based on array and Booth multiplier.