QUANTUM MECHANICAL MODELING OF CAPACITANCE- VOLTAGE AND CURRENT-VOLTAGE BEHAVIOR FOR SiO_2 AND HIGH-K DIELECTRICS

摘要

The requirements and methods for, and some results of accurate modeling of capacitance-voltage (CV) and current-voltage (IV) behavior in ultrathin effective oxide thickness (EOTs) SiO_2 and high-K gate dielectrics are discussed. It is demonstrated that rigorous quantum mechanical treatment of accumulation and strong-inversion layers is essential for accurate modeling of capacitance for gate dielectrics with EOTs approaching and below 1nm, and that because of the quantum mechanically enhanced capacitive contribution of the channel strong inversion layer alone, there is an ultimate approximately 0.2 nm limit to the electrical oxide thickness—the thickness that is relevant to the control of the conduction channel by the gate electrode—of MOS devices. It is demonstrated that self-consistent CV and IV calculations are essential for analysis of gate currents, and via such simulation, that the gate leakage current of at least the high-K gate stacks studied are consistent with direct tunneling of carriers through the gate dielectric.