Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA

摘要

In the paper, we present storage optimization scheme for hardware accelerating Needleman-Wunsch algorithm. The scheme exploits the characteristics of back-tracking phase in which the back-trace path only travels in a constrained area. Our analysis shows that in addition to logic element resource and memory capacity, the number of RAM blocks is also one of the constrained factors for hardware accelerating bio-sequence alignment. The optimized algorithm only store part of the score matrix to reduce storage usages of FPGA RAM blocks, and implement more processing element in FPGA. We fit our design on FPGA chips EP2S130 and XC2VP70. The experimental results show that the peak performance can reach 77.7 GCUPS (Giga cell updates per second) and 46.82 GCUPS respectively. Our implementation is superior to related works in clock frequency, the maximal PE number and peak performance, respectively.