A mechanism for implementing precise exceptions in pipelined processors

摘要

An exception is precise if all instructions before the faulting instruction have completed and those instructions following it can be restarted from scratch. If all exceptions in a processor are precise, the processor is said to implement the precise exception model. In a pipelined processor, precise exceptions can be difficult to achieve because an instruction may complete before its predecessors have completed. There exist several techniques for implementing precise exceptions, each varying in terms of performance and hardware cost. This paper introduces a novel solution to the precise exception problem and evaluates its predicted performance with respect to other schemes.