Minimizing voltage overshoot at the switchnode of a synchronous buck converter power stage enables use of a low side FET with a low voltage rating, reducing low side FET cost and/or dissipation. Inductance in the path that includes the input capacitor, high and low side FETs and the PCB traces connecting them was shown to contribute significantly to switch node ringing and voltage overshoot. The low side FET dram-source and gate-drain capacitances were identified as the capacitive elements of this tank circuit. Minimizing the ringing current loop area by locating high and low side FETs and a high frequency input capacitor as close together as possible was shown to increase the resonant frequency and decrease overshoot. Further reduction of overshoot by slowing high side FET excitation of the tank circuit was shown to have less efficiency penalty for a PCB implementation with a higher resonant frequency.
展开▼
