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HIGH DENSITY FLIP CHIP WITH ADHESIVES ON CERAMICS

机译:具有陶瓷粘合剂的高密度倒装芯片

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With regard to Mgh density and environmental-friendly chip-assembly processes, a new isotropic conductive adhesive (ICA) - non-conductive adhesive (NCA) flip chip technology was developed to meet those demands. This technology was already used on FH4 [1] and low-temperature substrates [2] with success. In this paper, the use of this ICA-NCA flip chip process on 96% Al{sub}2O{sub}3 will be described. A single layer test substrate has been made for a chip layout with staggered bonding pad layout and a pitch of 200μm. Four-point and daisy chain resistance measurement structures were available on this chip. Using standard thick-film screenprinting technologies, a conductive layer pitch below 250μm is difficult to achieve. In order to combine the high-density flip chip process with the thick-film technology, some other product had to be found. The product we used was the Heraeus KQ500 etchable gold conductor. The pitch of the flip chip assembly could easily be achieved with that gold conductor. The processing steps in that new flip chip assembly process are: the deposition and drying of the ICA, dispensing of the NCA, placement and thermocompression of the chip. In the area of thick film on ceramics, the speed and cost-effectiveness of the assembly process is very important. Therefore we believe we have developed a suitable process that takes into account all these demands.
机译:关于MGH密度和环境友好型芯片组装方法,开发出一种新的各向同性导电粘合剂(ICA) - 非导电粘合剂(NCA)倒装芯片技术以满足这些需求。该技术已经在FH4 [1]和低温基板上使用了成功。在本文中,将描述在96%Al {Sub} 2o {sub} 3上使用该ICA-NCA倒装芯片处理。已经制造了单层测试基板,用于芯片布局,具有交错键合焊盘布局和200μm的间距。在该芯片上可获得四点和菊花链电阻测量结构。使用标准厚膜筛印技术,难以实现低于250μm的导电层间距。为了将高密度倒装芯片过程与厚膜技术相结合,必须找到一些其他产品。我们使用的产品是Heraeus KQ500可蚀刻的金导体。通过该金导体可以容易地实现倒装芯片组件的间距。新的倒装芯片组装过程中的处理步骤是:ICA的沉积和干燥,芯片的NCA,放置和热压的分配。在陶瓷上的厚膜区域,装配过程的速度和成本效益非常重要。因此,我们相信我们已经制定了一个适当的过程,考虑了所有这些需求。

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