a compact signal processing architecture using a Nested Canonical Signed Digit (CSD) -Multiplier is described in this paper. The signal processor is a suitable solution for various kinds of filtering for two path purposes. The DSP could be used as a core without any basic changes for multi-channel applications with higher clock rates. It takes 0.35mm{sup}2 (RAM and ROM excluded) in a 0.35μm CMOS library.
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