This paper presents a low power register scheduling 'ation algorithm for multiple voltage. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which is not unnecessary the calculation through the extraction DFG from VHDL description. Also, low power register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. Finally, The total power reduced using the low power multiple voltage. The proposed algorithm proves the effect through various filter benchmark to adopt a low power register scheduling and allocation algorithm considering resource constraint at multiple voltage.
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