A novel front-end stage has been designed for use in solid state detector systems. Its novelty lies in the fact that it provides dual mode outputs: i) a voltage step that corresponds to the total integrated charge and ii) a fast differential signal that corresponds to the current pulse released by the detector. The first output signal is processed by a S-G shaper and is used for low/medium rate, low noise applications (peaking time 100ns, ENC=100e{sup}-@2pF external capacitance). The second one is used for high rate applications (peaking time 25ns, ENC=350e{sup}-@2pF external capacitance). The circuit has been implemented in 0.6μm CMOS process.
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