MODELING OF THE LEAKAGE DRAIN CURRENT IN ACCUMULATION-MODE SOI pMOSFETs FOR HIGH-TEMPERATURE APPLICATIONS

摘要

Nowadays, SOI CMOS technology is considered as the most suitable candidate for Integrated Circuits fabrication for high-temperatures applications (1), due to the drastic reduction of leakage currents at elevated temperatures when compared to the conventional CMOS technology (2). The aim of this work is to present a simple leakage drain current model for Accumulation-Mode SOI pMOSFETs operating from room up to 300°C, based on an equivalent circuit using two pairs of diodes and one resistor, which physically represents the transistor channel behavior in the leakage region. Measurements, MEDICI (3) and PSPICE (4) simulators were used to support our derivation.