Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the definition area, and by locating test vector related to abnormal IDDQ, following which fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.
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