Challenges in the extension of hierarchical wiring systems

摘要

Copper wiring and strongly hierarchical wiring schemes are capable, for now, of meeting performance needs for on-chip interconnections in CMOS logic. Based on a performance scaling scenario, future wiring demands can be estimated. Meeting these demands for 0.1 micrometer ground rules and beyond will pose many challenger for further improvement of the electrolytic-plating process which is used to fabricate the wiring.