Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays

摘要

A program for gate recognition has been developed and used to reduce the netlist produced by layout hat extraction of a I .2 million transistor bit-level systolic array design. The pipeline dynamic hip-flops as well as other elemental structures typical of systolic arrays are recognized. The netlist was reduced a factor 8, thus allowing a post-layout switch-level simulation of the whole chip, otherwise impossible on the original netlist.