A heterogeneous multiprocessing computer system with shared memory

摘要

A heterogeneous multiprocessing computer system constructed from microprocessors of different architectures is under development at CPHK. In this multiprocessing system, a cluster of processors of one architecture are connected through their system bus with a shared memory and a shared higher-level cache, which is named cluster cache. Such a cluster of processors is then connected to another similar cluster of processors of a different architecture with an asynchronous parallel bus through the cluster caches. This heterogeneous multiprocessing system supports distributed but shareable memory units. Each processor can access the memory on all processor clusters with programming transparency. Physical addresses are transmitted on the bus, with leading bits of the address to identify the target cluster. Data coherency of the cluster caches are strictly enforced. Thus the sharing of distributed memories of different systems is allowed. This paper reports the first phase of the project which includes the modeling of the asynchronous bus and the cluster cache memory with the VHSIC Hardware Description Language (VHDL).