A new write-invalidate snooping cache coherence protocol for split transaction bus-based multiprocessor systems

摘要

We present a new write-invalidate snooping cache coherence protocol called MMESSII cache protocol which addresses several significant drawbacks of existing write-invalidate snooping protocols under the split transaction bus based multiprocessor environment. In this protocol, each cache block maintains the ID information to identify the processor module that invalidated the block most recently. It also maintains seven cache states which consist of two updated states, one exclusive state, two shared states and two invalidated states. By using these states and the ID information, our protocol can reduce the contention for both memory modules and system bus significantly. We also present the simulation results which. Show better performance of our protocol than that of existing write-invalidate protocols.