Novel approach for nano-patterning magnetic tunnel junctions stacks: A route towards high density STT-RAM application

摘要

Summary form only given. Spin-Transfer-Torque Magnetic Random Access Memories (STT-RAM) based on out-of-plane magnetized MTJ (pMTJ) are one of the most promising emerging non-volatile memory technologies as they combine a unique set of assets: quasi-infinite write endurance, high speed, low power consumption and scalability. Embedded STT-MRAM are about to enter in volume production for e -FLASH replacement. For this type of applications not requiring very high memory density, the preferred etching technique is still Ion Beam etching (IBE) [1]. However this technique is not appropriate for high density memory as it requires to etch the MTJ stack at specific angles to minimize the re -deposition on the sidewalls of the tunnel junctions. Etching at some angle leads to shadowing effects which give to the pillars a conical shape. This effect worsens as the memory pitch shrinks below typically 5F resulting in a poor control of the critical dimension at very dense pitch. Besides it is difficult to implement on large wafer with good uniformity [2]. Reactive ion etching (RTE) was also tried for MTJs with various gas but was found to be very complex due to the heterogeneous nature of the MTJ stacks and to cause corrosion of the magnetic materials [3]. Therefore, to be able to use STT-RAM as a dense working memory requires a new method for nanopatteming MTJ elements at small feature size (<;20nm) and high pitch (-2F). In the approach we propose, the MTJ material is directly deposited on pre -patterned pillars (e.g Ta pillars prepared by RIB or Cu or W vias prepared by damascene process). The MTJ stack is then naturally patterned while being deposited thus not requiring any post -deposition etching. For the pre-pattemed non-magnetic posts, we chose Ta as post -material since its reactive ion etching is very well controlled. In order to avoid the risk of electrical shorts between pillars due to the material deposited in the trenches between posts, the latter are given an undercut shape. Thanks to this shape, during the MTJ deposition, no metal gets deposited on the pillar sidewalls nor at the foot of the metallic posts. The process for fabricating the conducting non-magnetic Ta posts with undercut is depicted in Fig. 1. Ta is coated by Pt to form the top part of the post and protect the top Ta surface from oxidation. Then, following the formation of cylindrical Ta/Pt posts by an anisotropic RIB process, an isotropic RIB process is subsequently used in order to laterally trim the Ta part of the posts. Perpendicular MTJ stacks with MgO barrier were then deposited on these pre -patterned substrates. By depositing the MgO tunnel barrier at oblique incidence while rotating the substrate, it is possible to completely coat the MTJ bottom electrode with MgO and even to get thicker MgO deposit on the sidewall of the bottom electrode than on the horizontal part of the MTJ. This can help to concentrate the current away from the edge of the nano -patterned MTJ thus reducing the influence of possible edge defects. Similarly, lateral gradient of chemical composition can be induced in the storage or reference layers. Such gradient can be used to induce different properties at the edges and center of each dot in order for instance to reduce demagnetizing or uncleation effects at edges and improve STT switching efficiency. The magnetic properties of pMTJ stacks deposited on the pre -patterned substrate were evaluated by focused Kerr microscopy. Half-MTJ stacks were fi rst deposited with bottom and top electrodes only to characterize the interfacial perpendicular anisotropy of the deposits on top of the posts CoFeB/MgO. The contribution of individual pillars and of the continuous deposit in the trenches could be distinguished. After optimizing the structural and magnetic properties, electrically characterization of these patterned MTJs were performed in terms of TMR and STT switching characteristics. The field-voltage switching phase diagram at room tempera