This paper analyzes the effect of bit error rate on ADC performance and presents triple modular redundancy method for data converters. A comparison among different analog to digital converters (including successive approximation register, algorithmic/cyclic, and pipeline ADC architectures) are discussed. It is shown that a multi-path architecture provides the ability to measure and correct bit errors, squaring the bit error performance without additional analog area or power. We provide a comparative study of bit error rate among the different architectures and an error power calculation method that may be applied to further variations on these architectures, without time-consuming transient simulations.
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