A Mathematical Model to assess the influence of parallelism in a Semiconductor Back-End Test Floor

摘要

The testing of IC at package level may require complex flows. In such cases, when the shop floor is fed with lots of multiple product lines, the manufacturing execution can suffer of very low efficiency, throughput limitation and longer cycle time than expected. The present work proposes a Mixed Integer Linear Programming model to evaluate the operational efficiency of the shop floor under different loading conditions and various shop floor characteristics. In particular, our computational campaign uses realistic data to evaluate the impact of increased parallelism and the effect of different parallelism distribution on the operational efficiency.