A Novel Method to Size Resistance for Biasing the POSFET Sensors in Common Drain Configuration

摘要

The fabrication process of POSFETs is based on customized NMOS/CMOS technology [1, 2] and is derived from an ISFET (i.e. ion-sensitive field-effect transistor)-based process [3]. Sensor chips consist of square arrays of N × N devices, with NMOS transistors implemented in p-well on n-substrate. A 4 μm aluminium layer (i.e. bottom metal layer) is over 45 nm thick interdigitized gate consisting of SiO_2/Si_3N_4. The PVDF-TrFE (i.e. piezoelectric polymer) is spin coated on the bottom metal layer, with top metal layer implemented with an alloy of gold after which the polymer is poled in situ. The POSFET chip based on NMOS and CMOS has p-well, whose junction depth is 4.76 μm and 8 μm, respectively, and the sheet resistance is 3.5 kΩ/sq in both processes. The specifications of POSFET chip based on the CMOS process are shown in Table 1. Additionally this POSFET chip features temperature-sensing diodes. The structural arrangement of POSFET (electrical model is shown in Fig. 1a) is similar to ISFET, as POSFET has a layer of piezoelectric polymer between metal plates on the gate of NMOS transistors, instead of ion-sensitive layer in the case of ISFET. Based on the work reported in [4], the arrangement of capacitances can be shown by Fig. 1b, where C_(PVDF) is the polymer capacitance and C_(gate) is the gate capacitance of the NMOS transistor.