Analysis of the Area-Delay Performance of Hybrid Nanoelectronic Memory Cores Used in Field Programmable Gate Arrays

摘要

In this paper, an area-delay metric (AT) of hybrid memristive/CMOS memory architectures is discussed. The proposed memory circuit can be used as a lookup table in field programmable gate arrays (FPGAs) and is modeled by a passive nanoelectronic crossbar comprising resistive switches (RS) as memory elements. In particular, resistive switches which are based on the electrochemical metallization effect (ECM) are assumed. At the periphery, CMOS circuits are included with provide appropriate voltage levels for robust read and write operations. The optimization of the CMOS periphery was done for a 40-nm CMOS technology, and especially in regard to the physical properties of ECM cells which allows for the derivation of a realistic AT metric for the memory core circuit. For different architectural choices, the evaluation of the AT metric shows, that the area overhead which is caused by the peripheral CMOS circuits significantly determines the total circuit area. Under almost all conditions the required silicon area per bit is far beyond 4F2 (F: lithographic resolution), but for particular conditions the effective area per bit is smaller than the area per bit which is required for a corresponding SRAM core circuit.