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Design of Verified Logic Control Programs

机译:验证逻辑控制程序的设计

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To complement the largely manual design of logic control programs in industrial practice, this contribution proposes a method for systematically (and partly algorithmically) deriving logic controllers for given specifications. The main idea is to structure the information available for the design in form of specific intermediate formats which are iteratively refined and straightforwardly lead to controllers formulated as Sequential Function Charts. To analyze whether the design complies with all given specifications, model-based verification is applied subsequently, i.e. the controller is converted into timed automata, the latter are composed with a plant model, and model-checking algorithmically verifies (or falsifies) logic properties for the composed system. The procedure is described here for the example of a multi-product batch plant.
机译:为了补充工业实践中的逻辑控制程序的主要手动设计,该贡献提出了一种用于系统(和部分算法)的方法,用于提供给定规范的逻辑控制器。主要思想是以特定中间格式的形式构建可用于设计的信息,该信息是迭代地精制和直接导致制定作为顺序功能图表的控制器。要分析设计是否符合所有给定的规范,随后应用基于模型的验证,即控制器被转换为定时自动机,后者由工厂模型组成,以及模型检查算法验证(或伪造)逻辑属性组成的系统。此处描述了用于多产品批量植物的示例的过程。

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