A new DAC circuit with multi-threshold voltage for large panel TFT-CLD source driver is proposed based on its binary-tree structural characters. Through setting different bulk voltages VB for different CMOS analog switches, the threshold voltages and the on-resistance of CMOS analog switches are reduced and the signal transmission speed from resistance network to output buffer is increased greatly. Physical implementation of this structure is simple and no extra components are required. The proposed DAC circuit structure with 10-bit resolution is designed and simulated using 0.35um 13.5V CMOS high-voltage process, the SPICE simulation results show that the step response delay time is reduced from 35ns to 17.4ns (by 50%), as compared to conventional DAC structure.
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