Scalable, Layered, Memory Protected Faulttolerance software architecture for Multi-Channel, Multi-Mode Radar Signal Processor for Active Array Radar using Multi Core Processor Hardware

摘要

The major advantage of Active Array Radar is its fault-tolerance capability i.e. the radar can still be operational with degraded performance even if some of the Transmit-Receive modules (TRM) fail in the system. Radar Signal Processor which receives digitized data from the data acquisition system and processes the data for various air-to-air, air-to-sea and air-to-ground mode of operation should not introduce single point failure in the system. The Radar signal processor, without fault-tolerance capability can make advantage of active array inattentive. The Radar Signal Processor for such requirement should have architecture which is scalable, layered, memory protected and fault-tolerant. This paper discusses about one such possible architecture.