This paper presents a method for designing SystemC-compliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper presents the ISS API and principles; then it describes how the same ISS can support SystemC simulation at several abstraction levels: untimed transaction level, approximately timed transaction level, and cycle accurate; then, it describes how the proposed ISS API has been used by six different laboratories - in the framework of the SoCLib project - to share the same L1 cache simulation model, and to wrap seven different processor cores in the same generic wrappers. Finally we demonstrate how the proposed API has been exploited to develop a generic debug and instrumentation infrastructure that can be used for all the processor cores, and all the abstraction levels supported by the SoCLib virtual prototyping platform.
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