New Architecture For NN Based Image Compression For Optimized Power, Area And Speed

摘要

The aim of this paper is to investigate new neural network algorithms, architectures and models which are inspired by the image processing capability of the visual system in the human brain, and subsequently to apply these models to medical imaging(MI) applications. Realizing the neural network architecture on FPGA that supports parallelism and reconfigurability. A sincere attempt is taken up to implement the complex and massive parallel architecture on FPGA optimising speed, area, and power with out compromising on image quality and SNR that is a very important criteria for medical image compression. Multi layered neural network (NN) architecture is proposed for compression of high-resolution image, the architecture is implemented on FPGA as it supports reconfigurability. The architecture considered has N-M-N (64-4-64) multi-layered NN structure, which achieves compression ratio of (CR) 93.75. Compression ratio is reconfigurable with change in M. The architecture is generalized and can achieve compression ratios from 2 to 99, which is reconfigurable. Performance of any neural network architecture for compression depends on training; this architecture considers general back propagation training. The training is performed offline, with known set of image samples consisting most of the properties of any standard image. The Mean Square Error (MSE) computed during every iteration of training is scaled and fed back into the network to update the weight matrix at specific points, this reduces the training time. As the weight matrix occupies more space for storage, the redundancies in the weight matrix are exploited and a storage space is created with minimum memory requirement on FPGA. Compression ratios obtained demonstrate performance superiority of the network as compared with JPEG compression standard. Inserting noise on the compressed sets of data, tests the network performance. The hardware complexity, area requirement, speed is compared and discussed; there is a saving of 22% of space on FPGA, with 40% increase in speed, and reducing the power by 12%. The major advantage of this architecture is its reconfigurability on the architecture size that achieves different compression ratios.