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Responsive Fault-Tolerant Computing in the era of Terascale Integration - State of Art Report

机译:TeraScale集成时代的敏感容错计算 - 艺术报告州

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Scaling in hardware integration process results in IC-process geometry reductions, lower operating voltages and increased clock speeds. This paper first surveys the reliability obstacles these developments give rise to and then points out that computing systems can no longer be safely assumed to fail only by crashing. Yet this assumption is at the core of primary-backup replication which the literature presents as the appropriate, and hence the most widely used, strategy for time-critical fault-tolerant applications. The paper then observes that building computing nodes with announced crash failure mode is a promising way forward to deal with the emerging reliability challenges. Work carried out to assure such a failure mode has also been briefly surveyed.
机译:在硬件集成过程中进行缩放导致IC-Process Geometry Deputions,更低的工作电压和增加的时钟速度。本文首先调查可靠性障碍这些发展引起的,然后指出计算系统可以不再通过崩溃来安全地失败。然而,这种假设是文献作为适当的初级备份复制的核心,因此使用最广泛使用的时间关键容错应用的策略。然后,该文件观察到具有宣布碰撞失败模式的建立计算节点是处理新兴的可靠性挑战的有希望的前途。已经进行了短暂的调查,以确保这种失败模式进行的工作。

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