The Effect of Package Pin Map on Signal Integrity for Test Applications

摘要

In the past decade the increasing signal speed of IC circuits has made the packaging design more challenging than ever. In order to deliver the signals from chip to PCB with minimal distortions, the signal integrity analysis has become a critical step of package design. Modern SI analysis tools have made it possible to analyze both package and PCB for signal integrity performance in order to achieve first pass system design success with ever-shrinking margins. However, the test socket has been mostly left out of such workflows of signal integrity analysis. The IC test engineers have been constantly challenged to develop test solutions where the system budget for the test sockets is rarely considered at design time. This paper examines the effects of package pin map on the signal integrity performance of the IC-socket-PCB system based on some real world case studies. The results clearly demonstrate that by including the socket into the system level design, the signal integrity performance of the package-socket-PCB system can be greatly improved. The paper also discusses the relationship between bandwidth, inductance, impedance and contact length.