3D vs. 2D analysis of FinFET logic gates under process variations

摘要

Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100–1000× reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (ION/IOFF) for a single device and leakage current or propagation delay (ILEAK/tD) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (LG), workfunction (ΦG) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of ILEAK/tD is quite small.