Digital configurable block based implementation of image enhancement algorithm using PSoC 5LP

摘要

In this paper four simple but very effective image enhancement technique is implemented in a digital configurable block on Programmable System on Chip (PSoC). This is done by converting a 2D gray image matrix to 1D vector and send it to PSoC5 LP Universal Asynchronous Receiver Transmitter (UART).The UART is communicating with a Verilog component which use Universal Digital Block Array (UDB) for implementing image enhancement algorithms. For implementing enhancement algorithm very simple Verilog components are developed by using Cypress PSoC Creator 2.2, It includes adder, subtracter, multiplier, 8 bit comparator, and multiplexer. Verilog components for constant values are also developed. Enhancement algorithms are implemented with the integration of arithmetic, logical and constant Verilog components.