High speed serial interface between image enhancement logic and ros for implementation of image enhancement algorithms

摘要

This circuit for serializing n parallel data bits requires that the data clock, having a clock period T, be used to generate n phased clocks of the same frequency as the data clock, but varying in phase such that each phased clock is delayed T/n with respect to the previous one. This can be done using a digital phase locked loop device. These n phased clocks and n parallel data bits are then input to a logic circuit which uses an n input Register and an n input multiplexer to output one data bit for each phased clock. The result is a serializer that converts parallel data to serial data without the need for generating a higher frequency clock.