Standard microcontrollers waste a significant amount of CPU cycles in order to handle I/O and peripheral resources. To handle communication between on-chip peripherals without interference from CPU, DMA or interrupt resources, the Atmel AVR XMEGA microcontroller introduces a peripheral resource known as the Event System. The Event System currently implemented on the AVR XMEGA offers limited resources for logical event computation, and can be used as a basic routing facility for I/O and peripheral signals. The present work proposes a novel extension to the Event System. In order to enhance routing flexibility a programmable asynchronous interconnect topology with pipelined switches has been designed, leading to increased computational power through the use of asynchronous LUTs to handle logical event computations.
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