CMOS logic circuits; NAND circuits; combinational circuits; delay circuits; finite state machines; logic design; power consumption; statistical analysis; transistors; NAND implementation; NAND2; active power consumption; average standard deviations; combinatorial building blocks; energy per operation; identical stacks; local variations; logic circuit delays; memory building blocks; modular layout-friendly digital cell library design; size 65 nm; static power consumption; statistical simulations; subthreshold CMOS operation; synchronous finite state machine; total active area; transistor slices; Delays; Layout; Libraries; Logic gates; Power demand; Standards; Transistors;
机译:物理亚阈值MOSFET建模应用于深亚微米全耗尽SOI低压CMOS技术的可行设计
机译:用于模拟/数字CMOS和BiCMOS专用集成电路设计的单元库和组装工具
机译:用于模拟/数字CMOS和BiCMOS专用集成电路设计的单元库和组装工具
机译:适用于亚阈值CMOS的模块化布局友好型单元库设计
机译:低功耗T-Gate单元库的设计与实现以及与其CMOS等效器件的比较。
机译:模块化ECMO仿真器的设计和实现
机译:适用于CMOS单元库的可测性策略的布局级设计
机译:用于单元库设计的最佳CmOs结构