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Time and Frequency Domain Tests for ΣΔ Modulators

机译:ΣΔ调制器的时间和频域测试

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The paper deals with the classification method of some architectures of ΣΔ modulators. The classification is based on the analysis of the different trends of the output signals characterizing some ΣΔ modulator architectures. The method operates (i) by feeding the ΣΔ modulator with sinusoidal signal, and (ii) by analysing the output signals in the time or in the frequency domain. The classification consists in (i) distinguishing between low pass and band pass ΣΔ modulator, (ii) identifying both the Single Quantizer Loop (SQL) and the Multistage Noise Shapers (MASH) architecture, (iii) evaluating the levels of the quantizer block inside the SQL architecture, and (iv) detecting the number of cascaded stage inside the MASH architecture. In order to validate the proposed method, numerical tests are performed by referring to the numerous architectures of ΣΔ modulators proposed in the relevant literature.
机译:本文涉及ΣΔ调制器的一些架构的分类方法。分类基于对特征一些ΣΔ调制器架构的输出信号的不同趋势的分析。该方法通过在时间或频域中分析输出信号来使用具有正弦信号的ΣΔ调制器和(ii)来操作(i)。分类包括在(i)中区分低通和带通ΣΔ调制器,(ii)识别单个量化器环路(SQL)和多级噪声整形器(MASH)架构(III)评估在内部的量化器块的级别SQL架构和(iv)检测醪架内级联阶段的数量。为了验证所提出的方法,通过参考相关文献中提出的ΣΔ调制器的许多架构来执行数值测试。

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