Modeling and Evaluation of a Shared Memory Design for a Mesh Topology NoC Architecture

摘要

One of the limitations of the current NOC architectures is their inability to provide efficient access mechanisms for on-chip or off-chip memories. It is expected that a large amount of memory will be required to support many cores on a NoC system. In this paper, we describe an efficient 3-level memory hierarchy suitable for NoC based systems. We also present a design of the memory network interface to connect a shared memory core to an on-chip network for block based accesses. We have developed a model of a mesh topology NoC architecture of size 5x5 with a single shared on-chip memory and buffer-less routers. The routers implement a very simple adaptive routing scheme. In the model five cores are made to concurrently access the shared memory for blocks of data. We have carried out interesting experiments to study the variation of average memory access time for different network loads, block size and width of a channel connecting two routers. As expected the average access time improves with the increase in the block size due to pipelined nature of memory accesses through the network. The results show that the average access time of the shared memory could be acceptable for block sizes larger than 100 bytes with channel widths of 64 bits even when the other traffic load is as much as 80%. However, it will be very slow to access blocks smaller than 32 bytes from a shared memory.