Discrete sliding mode control with overshot correction for interleaved VRM

摘要

In order to satisfy the new requirements of future microprocessors, the voltage regulator module should have high power densities, high efficiencies, good transient performance and tight output voltage tolerance. This paper presents a discrete-time sliding mode controller for an interleaved VRM due the good characteristics introduced to the complete system. This method presents an alternative control strategy that fulfill the fast dynamic response and limit the VRM output voltage variation under 2% tolerance during the large load transient generated by the processor. The analysis design and simulation are presented.