Design of Boundary Scan Master Based on PCB Test

摘要

SM (Boundary Scan Master) is the core device of BST controller. It will generate BST timing to control the whole testing process. Firstly, the functions of BSM are analyzed in this paper, we divide the BSM system into three parts: command interpreter, memory interface and JTAG interface, which provide BST. The detailed solutions of each part are presented. Then a completed BSM solution based on VHDL is realized, which has strong portability and can be used in both BST controller and common PCB design. It has been proved that the timing generated by this design is complying with IEEE 1149.1 standard by the computer simulation.