A MATLAB/SIMULINK TOOLBOX FOR THE SIMULATION-BASED HIGH-LEVEL SYNTHESIS OF NYQUIST-RATE DATA CONVERTERS - APPLICATION TO A PURE DIGITAL 0.13μm CMOS 12-bit@80MS/s ANALOG FRONT-END FOR PLC/VDSL

摘要

This paper presents a toolbox for the time-domain simulation and optimization-based high-level synthesis of Nyquist-rate data converters in MATLAB. Behavioural models of building blocks, including their critical non-idealities, are incorporated into SIMULINK as C-compiled S-functions. This approach significantly speeds up system-level simulations while keeping high accuracy and interoperability of different subcircuit models. Moreover, their combined use with an efficient optimizer makes the proposed toolbox a valuable alternative for the design of broadband communication analog front-ends. As a case study, an embedded 0.13μm CMOS 12bit@80MS/s A/D/A interface for PLC and VDSL is synthesized to show the capabilities of the presented tool.