Generating At-Speed array fail maps with low-speed ATE

摘要

A circuit has been developed to accurately generate embedded memory fail maps utilizing At-Speed test clocks generated from low-speed automated test equipment (ATE). The circuit provides a simple interface to communicate between the BIST and ATE for fail data collection. The BIST engine utilizes on-chip clock frequency multiplication to exercise the memory At-Speed. The described implementation reduces test time devoted to creating detailed fail maps in manufacturing by providing the ability to run the part At-Speed, and providing a means to collect fail map data in one test pass on a logic tester.