Real-time three-dimensional (3D) imaging represents a developing trend in medical imaging; however, most 3D medical imaging algorithms are computationally intensive. The first reason is the need to process massive amounts of data. For example, a 512{sup}3 8-bit image equates to 128 MB. The second reason is the complicated data addressing and accessing patterns used by 3D medical imaging algorithms, which do not allow for efficient fetching and managing of 3D image data using traditional word-line and interleave caching methods. These two reasons make implementation of 3D medical imaging algorithms time-consuming and expensive. In this paper, we present a reconfigurable SoC (system-on-chip) architecture and a 3D caching scheme, targeted to Virtex II Pro FPGAs, to accelerate a broad range of 3D medical imaging algorithms, typically dominated by local operations. To achieve high computational bandwidth, architectural parallelisms are exploited at three different levels: brick operation cycle, multiple parallel data-stream processing and deep pipeline architecture for data-stream processing.
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机译：实时三维（3D）成像代表了医学成像的发展趋势;然而，大多数3D医学成像算法是计算密集的。第一个原因是需要处理大量数据。例如，512 {sup} 3 8位图像等同于128 MB。第二个原因是3D医学成像算法使用的复杂数据寻址和访问模式，其不允许使用传统的字线和交错缓存方法有效地获取和管理3D图像数据。这两个原因使得实现3D医学成像算法耗时且昂贵。在本文中，我们介绍了一个可重构的SOC（片上系统）架构和一个针对Virtex II Pro FPGA的3D缓存方案，以加速广泛的3D医学成像算法，通常由本地操作主导。为了实现高计算带宽，架构并行性在三个不同的级别利用：砖件运行周期，多个并行数据流处理和用于数据流处理的深管线架构。
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