This paper introduces a CAD tool, ASPIRE (Automatic Spatial Partitioning In Reconfigurable Environments), for the spatial partitioning problem for Multi-FPGA architectures. The tool takes as input a HDL (Hardware Description Language) model of the application along with user specified constraints and automatically generates a task graph G; partitions the G based on the user specified constraints and maps the blocks of the partitions onto the different FPGAs (Field Programmable Gate Arrays) in the given Multi-FPGA architecture, all in a single-shot. ASPIRE uses an evolutionary approach for the partitioning step. ASPIRE handles the major part of the partitioning at the behavioral HDL level making it scalable with larger complex designs. ASPIRE was successfully employed to spatially partition a reasonably big cryptographic application that involved a 1024-bit modular exponentiation and to map the same onto a network of nine ACEX1K based Altera EP1K30QC208-1 FPGAs.
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