Modeling of Direct Tunneling Current in Multi-layer Gate Stacks

摘要

An analytical direct-tunneling gate current model for multi-layer gate dielectrics is presented. Theoretical derivation shows that the BSIM model for direct tunneling gate current through a single layer also works well for the multi-layer case. The theory is also supported by experimental data. This model is further extended to other modes of tunneling that occur at higher gate voltages. It has been shown that certain stack compositions result in higher leakage current depending on bias conditions. This model also predicts that the effectiveness of high-k dielectrics may decrease due to the reduction of band gap with increase in dielectric constant.