The Application Of A Dual-Substrate Technique On A 10-Gb/s CMOS Phase Detector Design

摘要

This paper presents a new dual-substrate technique used to overcome the small rail-to-rail supply voltage headroom available for short channel length CMOS technology. The technique is applied on a full-rate CMOS phase detector. (PD) for Synchronous Optical Network (SONET) OC-192 systems. A sample-and-hold PD for 10-Gb/s Non Return Zero (NRZ) data implemented in a standard 0.18μm CMOS technology is presented. The. measurement results show that a linear range with no dead zone on phase error from -π/2 toπ/2 is achieved. The core circuit dissipates a total power of 14.9 mW from a +/-1.6 V supply.